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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1997, 1999 mos integrated circuit m m m m pd16680 1/53, 1/40 duty, lcd controller/driver with built-in ram data sheet document no. s12694ej2v0ds00(2nd edition) date published july 1999 ns cp(k) printed in japan description the m pd16680 is a driver which contains a ram capable of full - dot lcd display. the single m pd16680 ic chip can operate a full - dot (up to 100 by 51 dots) lcd and pictographs (100 pictographs). the m pd16680 can operate on single 3 v-power supply, is suitable for graphic pagers and cellular. features lcd driver with a built-in display ram can operate on single 3 v-power supply booster circuit incorporated : switchable 3 or 4 folds dot display ram : 100 x 51 bits pictographic display ram : 100 bits pictographic display's duty changeable : 1/53 or 1/40 duty output for full-dot : 100 segments and 52 commons data input based on serial & 4-bit / 8-bit parallel switch over string resister to output bias level incorporated selectable lcd driving bias level (select from 1/8 bias, 1/7 bias, 1/6 bias) oscillation circuit incorporated d/a converter incorporated (for lcd driving voltage adjustment) ordering information part number package m pd16680w/p wafer/chip(matched cog mounting) remark purchasing the above products in term of chips per requires an exchange of other documents as well, including a memorandum on the product quality. therefore those who are interested in this regard are advised to contact an nec salesperson for further details. the mark ? ? ? ? shows major revised points.
data sheet s12694ej2v0ds00 2 m m m m pd16680 1. block diagram stb e(sck) ws d 7 (ns) c 1 , c 1 i/o buffer timing generator c 2 + , c c 3 , c 3 v ext dc/dc oscillator circuit converter d/a converter blink controller op amp v lc1 v lc2 v lc3 v lcbs2 v lcbs1 v lcbs3 v lc4 v lc5 command decoder address decoder data register display data ram 100 x 51 bits pictograph data ram 100 bits blink data ram 100 bits lcd voltage generator 100-bit latch 53-bit register common driver segment driver com 0 com 51 pcom seg 1 seg 100 100 100 v lcd v dd d 1 d 6 test out /reset d 0 ( data ) to + - 2 - + - v ss osc out osc in osc bri da cha amp in(+) amp in(-) amp out amp cha remark /xxx indicates active low si gnals.
data sheet s12694ej2v0ds00 3 m m m m pd16680 2. pin configuration (top view) chip size : 12.5 mm x 1.89 mm 249 250 264 1 99 100 114 115 x y
data sheet s12694ej2v0ds00 4 m m m m pd16680 table 2-1. pad layout (1/2) pin no. pin name x( m m) y( m m) pin no. pin name x( m m) y( m m) 1 dummy C5883.2 C811.0 67 c 3 + 2036.8 C811.0 2 dummy C5763.2 C811.0 68 c 3 + 2156.8 C811.0 3 dummy C5643.2 C811.0 69 c 3 + 2276.8 C811.0 4v lcbs1 C5523.2 C811.0 70 c 3 C 2396.8 C811.0 5v lcbs1 C5403.2 C811.0 71 c 3 C 2516.8 C811.0 6 dummy C5283.2 C811.0 72 c 3 C 2636.8 C811.0 7v lcbs2 C5163.2 C811.0 73 v dd 2756.8 C811.0 8v lcbs2 C5043.2 C811.0 74 v dd 2876.8 C811.0 9 dummy C4923.2 C811.0 75 v dd 2996.8 C811.0 10 v lcbs3 C4803.2 C811.0 76 dummy 3116.8 C811.0 11 v lcbs3 C4683.2 C811.0 77 v ext 3236.8 C811.0 12 dummy C4563.2 C811.0 78 da cha 3356.8 C811.0 13 amp out C4443.2 C811.0 79 amp cha 3476.8 C811.0 14 amp out C4323.2 C811.0 80 osc in 3596.8 C811.0 15 dummy C4203.2 C811.0 81 osc out 3716.8 C811.0 16 amp in(-) C4083.2 C811.0 82 v dd 3836.8 C811.0 17 amp in(-) C3963.2 C811.0 83 osc bri 3956.8 C811.0 18 dummy C3843.2 C811.0 84 d 0 (data) 4076.8 C811.0 19 amp in(+) C3723.2 C811.0 85 d 1 4196.8 C811.0 20 amp in(+) C3603.2 C811.0 86 d 2 4316.8 C811.0 21 dummy C3483.2 C811.0 87 d 3 4436.8 C811.0 22 v dd C3363.2 C811.0 88 d 4 4556.8 C811.0 23 v dd C3243.2 C811.0 89 d 5 4676.8 C811.0 24 dummy C3123.2 C811.0 90 d 6 4796.8 C811.0 25 v lc5 C3003.2 C811.0 91 d 7 (ns) 4916.8 C811.0 26 v lc5 C2883.2 C811.0 92 ws 5036.8 C811.0 27 v lc5 C2763.2 C811.0 93 stb 5156.8 C811.0 28 dummy C2643.2 C811.0 94 e(sck) 5276.8 C811.0 29 v lc4 C2523.2 C811.0 95 /reset 5396.8 C811.0 30 v lc4 C2403.2 C811.0 96 v dd 5516.8 C811.0 31 v lc4 C2283.2 C811.0 97 test out 5636.8 C811.0 32 dummy C2163.2 C811.0 98 dummy 5756.8 C811.0 33 v lc3 C2043.2 C811.0 99 dummy 5876.8 C811.0 34 v lc3 C1923.2 C811.0 100 dummy 6112.0 C682.2 35 v lc3 C1803.2 C811.0 101 dummy 6112.0 C592.2 36 dummy C1683.2 C811.0 102 com 27 6112.0 C502.2 37 v lc2 C1563.2 C811.0 103 com 28 6112.0 C412.2 38 v lc2 C1443.2 C811.0 104 com 29 6112.0 C322.2 39 v lc2 C1323.2 C811.0 105 com 30 6112.0 C232.2 40 dummy C1203.2 C811.0 106 com 31 6112.0 C142.2 41 v lc1 C1083.2 C811.0 107 com 32 6112.0 C52.2 42 v lc1 C963.2 C811.0 108 com 33 6112.0 37.8 43 v lc1 C843.2 C811.0 109 com 34 6112.0 127.8 44 dummy C723.2 C811.0 110 com 35 6112.0 217.8 45 v lcd C603.2 C811.0 111 com 36 6112.0 307.8 46 v lcd C483.2 C811.0 112 com 37 6112.0 397.8 47 v lcd C363.2 C811.0 113 dummy 6112.0 487.8 48 v dd C243.2 C811.0 114 dummy 6112.0 577.8 49 v dd C123.2 C811.0 115 dummy 6030.0 817.8 50 v dd C3.2 C811.0 116 dummy 5940.0 817.8 51 v ss 116.8 C811.0 117 com 38 5850.0 817.8 52 v ss 236.8 C811.0 118 com 39 5760.0 817.8 53 v ss 356.8 C811.0 119 com 40 5670.0 817.8 54 dummy 476.8 C811.0 120 com 41 5580.0 817.8 55 c 1 + 596.8 C811.0 121 com 42 5490.0 817.8 56 c 1 + 716.8 C811.0 122 com 43 5400.0 817.8 57 c 1 + 836.8 C811.0 123 com 44 5310.0 817.8 58 c 1 C 956.8 C811.0 124 com 45 5220.0 817.8 59 c 1 C 1076.8 C811.0 125 com 46 5130.0 817.8 60 c 1 C 1196.8 C811.0 126 com 47 5040.0 817.8 61 c 2 + 1316.8 C811.0 127 com 48 4950.0 817.8 62 c 2 + 1436.8 C811.0 128 com 49 4860.0 817.8 63 c 2 + 1556.8 C811.0 129 com 50 4770.0 817.8 64 c 2 C 1676.8 C811.0 130 com 51 4680.0 817.8 65 c 2 C 1796.8 C811.0 131 pcom 4590.0 817.8 66 c 2 C 1916.8 C811.0 132 seg 100 4500.0 817.8
data sheet s12694ej2v0ds00 5 m m m m pd16680 table 2-1. pad layout (2/2) pin no. pin name x( m m) y( m m) pin no. pin name x( m m) y( m m) 133 seg 99 4410.0 817.8 199 seg 33 C1530.0 817.8 134 seg 98 4320.0 817.8 200 seg 32 C1620.0 817.8 135 seg 97 4230.0 817.8 201 seg 31 C1710.0 817.8 136 seg 96 4140.0 817.8 202 seg 30 C1800.0 817.8 137 seg 95 4050.0 817.8 203 seg 29 C1890.0 817.8 138 seg 94 3960.0 817.8 204 seg 28 C1980.0 817.8 139 seg 93 3870.0 817.8 205 seg 27 C2070.0 817.8 140 seg 92 3780.0 817.8 206 seg 26 C2160.0 817.8 141 seg 91 3690.0 817.8 207 seg 25 C2250.0 817.8 142 seg 90 3600.0 817.8 208 seg 24 C2340.0 817.8 143 seg 89 3510.0 817.8 209 seg 23 C2430.0 817.8 144 seg 88 3420.0 817.8 210 seg 22 C2520.0 817.8 145 seg 87 3330.0 817.8 211 seg 21 C2610.0 817.8 146 seg 86 3240.0 817.8 212 seg 20 C2700.0 817.8 147 seg 85 3150.0 817.8 213 seg 19 C2790.0 817.8 148 seg 84 3060.0 817.8 214 seg 18 C2880.0 817.8 149 seg 83 2970.0 817.8 215 seg 17 C2970.0 817.8 150 seg 82 2880.0 817.8 216 seg 16 C3060.0 817.8 151 seg 81 2790.0 817.8 217 seg 15 C3150.0 817.8 152 seg 80 2700.0 817.8 218 seg 14 C3240.0 817.8 153 seg 79 2610.0 817.8 219 seg 13 C3330.0 817.8 154 seg 78 2520.0 817.8 220 seg 12 C3420.0 817.8 155 seg 77 2430.0 817.8 221 seg 11 C3510.0 817.8 156 seg 76 2340.0 817.8 222 seg 10 C3600.0 817.8 157 seg 75 2250.0 817.8 223 seg 9 C3690.0 817.8 158 seg 74 2160.0 817.8 224 seg 8 C3780.0 817.8 159 seg 73 2070.0 817.8 225 seg 7 C3870.0 817.8 160 seg 72 1980.0 817.8 226 seg 6 C3960.0 817.8 161 seg 71 1890.0 817.8 227 seg 5 C4050.0 817.8 162 seg 70 1800.0 817.8 228 seg 4 C4140.0 817.8 163 seg 69 1710.0 817.8 229 seg 3 C4230.0 817.8 164 seg 68 1620.0 817.8 230 seg 2 C4320.0 817.8 165 seg 67 1530.0 817.8 231 seg 1 C4410.0 817.8 166 seg 66 1440.0 817.8 232 com 26 C4500.0 817.8 167 seg 65 1350.0 817.8 233 com 25 C4590.0 817.8 168 seg 64 1260.0 817.8 234 com 24 C4680.0 817.8 169 seg 63 1170.0 817.8 235 com 23 C4770.0 817.8 170 seg 62 1080.0 817.8 236 com 22 C4860.0 817.8 171 seg 61 990.0 817.8 237 com 21 C4950.0 817.8 172 seg 60 900.0 817.8 238 com 20 C5040.0 817.8 173 seg 59 810.0 817.8 239 com 19 C5130.0 817.8 174 seg 58 720.0 817.8 240 com 18 C5220.0 817.8 175 seg 57 630.0 817.8 241 com 17 C5310.0 817.8 176 seg 56 540.0 817.8 242 com 16 C5400.0 817.8 177 seg 55 450.0 817.8 243 com 15 C5490.0 817.8 178 seg 54 360.0 817.8 244 com 14 C5580.0 817.8 179 seg 53 270.0 817.8 245 com 13 C5670.0 817.8 180 seg 52 180.0 817.8 246 com 12 C5760.0 817.8 181 seg 51 90.0 817.8 247 com 11 C5850.0 817.8 182 seg 50 0.0 817.8 248 dummy C5940.0 817.8 183 seg 49 C90.0 817.8 249 dummy C6030.0 817.8 184 seg 48 C180.0 817.8 250 dummy C6112.0 577.8 185 seg 47 C270.0 817.8 251 dummy C6112.0 487.8 186 seg 46 C360.0 817.8 252 com 10 C6112.0 397.8 187 seg 45 C450.0 817.8 253 com 9 C6112.0 307.8 188 seg 44 C540.0 817.8 254 com 8 C6112.0 217.8 189 seg 43 C630.0 817.8 255 com 7 C6112.0 127.8 190 seg 42 C720.0 817.8 256 com 6 C6112.0 37.8 191 seg 41 C810.0 817.8 257 com 5 C6112.0 -52.2 192 seg 40 C900.0 817.8 258 com 4 C6112.0 -142.2 193 seg 39 C990.0 817.8 259 com 3 C6112.0 -232.2 194 seg 38 C1080.0 817.8 260 com 2 C6112.0 -322.2 195 seg 37 C1170.0 817.8 261 com 1 C6112.0 -412.2 196 seg 36 C1260.0 817.8 262 pcom C6112.0 -502.2 197 seg 35 C1350.0 817.8 263 dummy C6112.0 -592.2 198 seg 34 C1440.0 817.8 264 dummy C6112.0 -682.2
data sheet s12694ej2v0ds00 6 m m m m pd16680 3. pin descriptions 3.1 power system pins pin symbol pin name pin no. i/o function description v dd logic and booster power supply pin 22, 23, 48 to 50, 73 to 75, 82, 96 - power supply pin for logic and booster circuit. v ss logic and driver ground pin 51 to 53 - ground pin for logic and driver circuit. v lcd driver power supply pin 45 to 47 - driver power supply pin. output pin of internal booster circuit. please connect with a 1 m f booster capacitor to ground. when not using the internal booster circuit, the driver power can be turned on directly. v lc1 to v lc5 driver reference power supply 25 to 27, 29 to 31, 33 to 35, 37 to 39, 41 to 43 - reference power supply pin for lcd drive. when the internal bias is selected, be sure to leave it open. when display contrast is bad, connect a capacitor between these pins and ground. v lcbs1 to v lcbs3 bias level select pin 4, 5, 7, 8, 10, 11 - when the internal bias is selected, connecting these pins outside the ic, the bias level can be changed. c 1 + , c 1 C c 2 + , c 2 C c 3 + , c 3 C capacitor connection pins 55 to 72 - capacitor connection pins for booster circuit. when using internal booster circuit, connect a 1 m f capacitor between these pins. h
data sheet s12694ej2v0ds00 7 m m m m pd16680 3.2 logic system pins (1/2) pin symbol pin name pin no. i/o function description ws word length select pin (word select) 92 i this pin selects the word length. at high level, it become an 8-bit parallel interface. at low level, when d 7 (ns) is high level, it become a serial interface. when the word length is 4 bits, data is transferred in the upper-to-low sequence by mean of data busses d 0 to d 3 . the word length cannot be changed after power-on. da cha d/a converter select pin 78 i this pin selects whether to use the internal d/a converter for lcd driving voltage adjustment or not. at high level, d/a converter is used. at low level, unused. stb strobe 93 i this pin is select signal of device, strobe signal for data transfer. data transfer is initialized at falling/rising edge of stb. data can be input/output at low level either in parallel interface or serial interface mode. when stb is high level, enable/shift clock is bypassed. e(sck) enable(shift clock) 94 i when using parallel interface mode, this pin becomes the data enable input. in reading-in, data is fetched into the interface buffer at rising edge. in reading-out, data is fetched from interface buffer at falling edge. when using serial interface mode, this pin becomes the data shit clock. in reading-in, data is fetched into the interface buffer at rising edge. in reading-out, data is fetched from interface buffer at falling edge. d 0 (data) data-bus(data) 84 i/o when using parallel interface mode, this pin becomes the d 0 bit of data-bus. when using serial interface mode, this pin becomes the input/output pin of the command and display data (3 states). d 1 to d 3 data-bus 85 to 87 i/o when using parallel interface mode, these pin becomes the d 1 to d 3 bits of data-bus. when using serial interface mode, keep them h or l. d 4 to d 6 data-bus 88 to 90 i/o when using parallel interface mode, these pin become the d 4 to d 6 bits of data-bus. when using serial interface mode, keep them h or l. d 7 (ns) data-bus(nibble select) 91 i/o when word select (ws) is high level, this pin becomes the d 7 bit of data-bus. when word select (ws) is low level, this pin becomes nibble select pin. at high level, selected 4-bit parallel interface. at low level, selected serial interface. test out test signal output 97 o when to do test, this pin is output for test signal. when using in normal operation, this pin leave open. /reset reset 95 i at low level, the m pd16680 is initialized.
data sheet s12694ej2v0ds00 8 m m m m pd16680 3.2 logic system pins (2/2) pin symbol pin name pin no. i/o function description amp cha amp mode select pin 79 i select operational amplifier mode. at high level, level capacitor mode. at low level, lcd driving mode. v ext lcd reference supply switching 77 i select the method for supplying lcd power circuit. at high level, lcd driving voltage is supplied external circuit. at low level, it is supplied internal circuit. osc in 80 i osc out oscillation pin 81 o these pins are connected with the 1 m w resistor. when using external oscillation, input into the osc in , and leaving the osc out open. osc bri blinking clock 83 i this pin is oscillation input for blinking. to input 2 hz external clock, when to use blinking by external clock mode. when not to use this pin, keep it h or l.
data sheet s12694ej2v0ds00 9 m m m m pd16680 3.3 driver system pins pin symbol pin name pin no. i/o function description seg 1 to seg 100 segment 132 to 231 o segment output pins. com 1 to com 51 common 102 to 112, 117 to 130, 232 to 247, 252 to 261 o common output pins pcom pictographic common 131, 262 o common output pins for pictograph. (same waveform output from these pins.) amp in (+) 19, 20 amp in (-) operational amplifier input 16,17 i these pins are the input pins of operational amplifier for lcd driving voltage adjustment. when using the internal d/a converter, leave amp in(+) open. when not using the internal d/a converter, it is necessary to input the reference voltage. amp in(C) is connected to the resister for lcd driving voltage adjustment. see 4. lcd driving voltage control circuit . amp out operational amplifier output 13,14 o this is the input pin of operational amplifier for lcd driving voltage adjustment. normally it is connected to the resister for lcd driving voltage adjustment. see 4. lcd driving voltage control circuit . it recommends to connect to this pin a 0.1 to 1 m f capacitor to make the output of the internal operational amplifier be stable. dummy dummy pad 1, 2, 3, 9, 12, 15, 18, 21, 24, 28, 32, 33, 40, 44, 54, 76, 98 to 101, 113 to 116, 248 to 251, 263, 264 - dummy pins are not connected to the internal circuit. leave open if they are not used. 4. lcd driving voltage control circuit reference power circuit d/a converter da cha amp in(+) amp in( - ) amp out v lc1 v ss v ext r 2 r 1 c 1 - v lc2 v lc3 v lc4 v lc5 v lcbs1 v lcbs2 v lcbs3 +
data sheet s12694ej2v0ds00 10 m m m m pd16680 5. power circuit the m pd16680 incorporate the booster circuit is switchable between 3 and 4 folds. the boosting magnitude of internal booster circuit is selected by the capacitor connection. the reference power circuit is switchable between internal driving circuit and external driving circuit. the method for supplying the reference circuit selected by v ext pin (h : external, l : internal ). 5.1 booster circuit using internal driving circuit, to connect condenser for boosting between c 1 + and c 1 C , c 2 + and c 2 C , c 3 + and c 3 C , to connect condenser between v lcd and v dd to be stable boosting voltage. and to set v ext pin to low level, internal booster circuit boost voltage between v dd and v ss to 3 or 4 folds. the booster circuit is using clock made by internal oscillation circuit. it is necessary that oscillation to be operated. c 1 + , c 1 C ,c 2 + ,c 2 C ,c 3 + ,c 3 C , v dd are pins for booster circuit. to use the wire that have low register value to connect these pins. figure 5-1 3x and 4x booster circuits v dd = 3 v v ss = 0 v v lcd = 3v dd = 9 v (3-fold boost) v lcd = 4v dd = 12 v (4-fold boost) remarks 1. when to use 3-fold booster circuit, not to connect condenser between c 3 + and c 2 C , c 1 + and c 1 C , leave open c 2 + and c 3 C . 2. when to use external power supply circuit, booster circuit is not operating.
data sheet s12694ej2v0ds00 11 m m m m pd16680 5.2 lcd driving circuit 5.2.1 to use internal driving circuit, not to use d/a converter ( v ext = l , da cha = l ) when to internal driving circuit is chosen, boosted voltage be used for power of internal operational amplifier adjusting lcd driving voltage. to connect external resister r 1 , r 2 , and input reference voltage to amp in (+) pin. it is possible to adjust lcd driving voltage of v lc1 . if using thermistor to adjust lcd driving voltage according to the temperature characteristic of lcd panel, we recommend connecting it with r 2 in parallel. the value of v lc1 can be computed by the following formula. equation 5-1 v lc1 = amp in (+) = (1+ ) v ref remark r 2 = figure 5-2 when not using internal power supply select or d/a converter v ref to internal driving circuit d/a converter amp in(-) amp out v lc1 r 2 r 1 r th amp in(+) da cha + - c 1 r 2 r 1 r 2 x r th r 2 + r th
data sheet s12694ej2v0ds00 12 m m m m pd16680 5.2.2 to use internal driving circuit and d/a converter ( v ext = l , da cha = h ) to use d/a converter, it is possible to adjust reference voltage v ref inputted to amp in (+) pin for lcd driving by command. to set 6-bit data to d/a converter register, reference voltage v ref is choose one level from 64 level in 1/2 v dd to v dd . the formula of v lc1 is as same written in equation 5-1 . figure 5-3 using internal power supply select and d/a converter v dd v dd to internal driving circuit d/a converter amp in(-) amp out v lc1 r 2 r 1 c 1 + - r th amp in(+) da cha open v ref . 5.2.3 to use external driving circuit ( v ext = h ) when external voltage supply circuit for lcd driving is chosen, operational amplifier incorporated ic is off. therefore, it is impossible to use operational amplifier for lcd driving and d/a converter function. lcd driving voltage is adjust by the voltage inputted to v lcd and v lc1 pins directly. remarks 1. set v lcd 3 v lc1. 2. da cha , amp in (+) , amp in (-) are cmos input. set h level or l level. 3. set amp out pin "open".
data sheet s12694ej2v0ds00 13 m m m m pd16680 5.3 reference voltage circuit 5.3.1 to use internal reference voltage circuit ( v ext = l ) when internal driving circuit is chosen, 6 levels for lcd reference voltage (v lc1 , v lc2 , v lc3 , v lc4 , v lc5 , v ss ) is generate by internal breeder resister. 5.3.2 to use external driving circuit ( v ext = h ) when external driving circuit is chosen, operational amplifier incorporated ic is off. it is necessary to input voltage to v lc1 , v lc2 , v lc3 , v lc4 and v lc5 directly. generally, these levels are made by external breeder resister. the display dignity of lcd declines when these resistance values are big, it is necessary to choose the resistance value which corresponds with the lcd panel. there is an effect that improves display dignity when connecting a capacitor with each level pins and the ground. it is necessary to choose the condenser value which corresponds with the lcd panel. figure 5-3. reference voltage circuit v lc1 r to seg, com outputs v lc2 r to com output v lc3 r to seg output r r v lcbs3 v lcbs2 v lc4 r to seg output v lc5 - r to com output amp out to seg, com output v lcbs1 v ss voltage follower for level voltage + - + - + - + - + h
data sheet s12694ej2v0ds00 14 m m m m pd16680 5.4 setting bias value when internal driving circuit chosen, by connecting the interval of the pin v lcbs1 , v lcbs2 , v lcbs3 outside the ic, the bias value can be set from the 1/6 bias, the 1/7 bias, the 1/8 bias. bias value pin connection 1/8 bias v lcbs1 , v lcbs2 , v lcbs3 all open 1/7 bias to connect v lcbs1 and v lcbs2 , or v lcbs2 and v lcbs3 1/6 bias to connect v lcbs1 and v lcbs3 , v lcbs2 is open. 5.5 voltage followers for level power supply by the input of amp cha pin, it controls voltage follower for the lcd drive level power supply. lcd driving mode ( amp cha = l ) when this mode is chosen, the voltage follower maximizes electric current supply ability for lcd drive. it doesn't need to connect the external capacitor for the level stability. level capacitor mode ( amp cha = h ) when this mode is chosen, the voltage follower maximizes electric current supply ability for the external condenser charging. in this mode, it needs to connect the external capacitor ( 0.1 to 1.0 m f ) for the level stability. caution when using this mode without connecting capacitor, the display dignity will be bad.
data sheet s12694ej2v0ds00 15 m m m m pd16680 5.6 application circuit example 5.6.1 to use internal driving circuit, lcd driving mode v dd v dd v lcd c 1 c 1 c 2 c 2 c 3 c 3 v ss v ext v ss v ext amp cha v lc5 v lc4 v lc3 v lc2 v lc1 amp out amp in( - ) amp in(+) c 2 c 1 c 1 c 1 v lcd c 3 open c 2 c 1 + + + + + c 1 c 2 c 3 open c 2 c 1 c 1 + + + + - + - + - - + + - - + a) boost 4folds (not to use d/a converter) b) boost 3 folds v dd note1 note2 note2 open r1 r2 rth(thermistor) notes 1. when to use d/a converter, amp in(+) is open. 2. c 2 + , c 3 C are open. remark c1 = c2 = 1.0 m m
data sheet s12694ej2v0ds00 16 m m m m pd16680 5.6.2 to use internal driving circuit, lcd driving mode v dd v dd v dd v lcd c 1 c 1 c 2 c 2 c 3 c 3 v ss v ext v lc5 v lc4 v lc3 v lc2 v lc1 c 2 c 1 c 1 c 1 v lcd c 3 open v ext v ss c 2 c 1 + + + + c 1 c 2 c 3 open c 2 c 1 c 1 + + + + + + + + + + - + - + - - + + - - + a) boost 4folds(not to use d/a converter) b) boost 3 folds amp out amp cha amp in( - ) amp in(+) v dd r1 r2 rth(thermistor) note1 note2 note2 notes 1. when to use d/a converter, amp in(+) is open. 2. c 2 + , c 3 C are open. remark c1 = c2 = 1.0 m m
data sheet s12694ej2v0ds00 17 m m m m pd16680 5.6.3 to use external driving circuit v dd v dd c 1 c 1 c 2 c 2 c 3 c 3 v ss v ext v lc5 v lc4 v lc3 v lc2 v lc1 v lcd amp out amp in( - ) amp in(+) + - + - + - to use 1/6 bias open open r r 2r r r external power supply
data sheet s12694ej2v0ds00 18 m m m m pd16680 6. lcd driving the m pd16680 is able to choose duty 1/53 duty or 140 duty. 6.1 1/53 duty driving when 1/53 duty is chosen, the m pd16680 outputs a choice signal once at 1 frame from the dot part common outputs (com 1 to com 51 ), the pictograph part common outputs (pcom). 12345678 515253 12345678 515253 v lc1 v lc2 v lc3 v lc4 v lc5 v ss seg 1 v lc1 v lc2 v lc3 v lc4 v lc5 v ss com 2 v lc1 v lc2 v lc3 v lc4 v lc5 v ss com 1 v lc1 v lc2 v lc3 v lc4 v lc5 v ss pcom 1 frame
data sheet s12694ej2v0ds00 19 m m m m pd16680 6.2 1/40 duty driving when 1/40 duty is chosen, the m pd16680 outputs a choice signal once at 1 frame from the dot part common outputs (com 1 to com 19 , com 27 to com 45 ), the pictograph part common outputs (pcom ). 12345678 383940 12345678 383940 v lc1 v lc2 v lc3 v lc4 v lc5 v ss seg 1 v lc1 v lc2 v lc3 v lc4 v lc5 v ss com 2 v lc1 v lc2 v lc3 v lc4 v lc5 v ss com 1 v lc1 v lc2 v lc3 v lc4 v lc5 v ss pcom 1 frame
data sheet s12694ej2v0ds00 20 m m m m pd16680 7. lcd display the m pd16680 can display 100 by 51 dots (called full-dot display) lcd display and 100 pictographs. figure 7-1 lcd matrix pcom com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 16 com 17 com 18 com 19 com 47 com 48 com 49 com 50 com 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 89 90 91 92 93 94 95 96 97 98 99 100
data sheet s12694ej2v0ds00 21 m m m m pd16680 8. group addresses 8.1 dot display the group addresses of dot display are assigned as follows. to be chosen the address is increment, when x address goes to 0ch, next address is 00h. at this time, y address goes to next address. when y address goes to 33h, next address is 00h, too. 00h 01h 02h 33h 01h 02h 0bh 0ch x address 00h 03h 32h x x x x y address b7 b6 b5 b4 b7 b6 b5 b4 b3 b2 b1 b0 remark data of x address = 0ch : b7 to b4 are data, b3 to b0 are don't care. when 1/53 duty and using 1/40 duty are used, the ram addresses and the common pins used are as follows. duty use ram y addresses dont use ram y addresses use common pins dont use common pins 1/53 duty 00h to 33h - com1 to com51 - 1/40 duty 00h to 12h 1ah to 2ch note 13h to 19h 2dh to 33h com1 to com19 com27 to com45 com20 to com26 com46 to com51 note if address incrementation is set when 1/40 duty is used, the x address value following 0ch is 00h. at the same time the y address is incremented by 1. the y address value following 12h is 1ah, and the value following 2ch is 00h. h
data sheet s12694ej2v0ds00 22 m m m m pd16680 8.2 pictograph the group addresses of pictograph are assigned as follows. to be chosen the address is increment, x address goes to 0ch, next address is 00h. (pcom) x address b7 8 bits 00h 01h 02h 03h b6 b5 b4 b3 b2 b1 b0 00h 0bh 0ch y address table 8-1 pcom (y address = 00h) segment output no. x address b7 b6 b5 b4 b3 b2 b1 b0 00h 12345678 01h 910111213141516 02h 17 18 19 20 21 22 23 24 03h 25 26 27 28 29 30 31 32 04h 33 34 35 36 37 38 39 40 05h 41 42 43 44 45 46 47 48 06h 49 50 51 52 53 54 55 56 07h 57 58 59 60 61 62 63 64 08h 65 66 67 68 69 70 71 72 09h 73 74 75 76 77 78 79 80 0ah 8182838485868788 0bh 8990919293949596 0ch 979899100xxxx remark data of x address = 0ch :b7 to b4 are data, b3 to b0 are dont care.
data sheet s12694ej2v0ds00 23 m m m m pd16680 8.3 blink data the group addresses of brink data are assigned as follows. to be chosen the address is increment, when x address goes to 0ch, next address is 00h. (pcom) x address b7 8 bits 00h 01h 02h 03h b6 b5 b4 b3 b2 b1 b0 00h 0bh 0ch y address table 8-2 pcom (y address = 00h) segment output no. x address b7 b6 b5 b4 b3 b2 b1 b0 00h 12345678 01h 910111213141516 02h 17 18 19 20 21 22 23 24 03h 25 26 27 28 29 30 31 32 04h 33 34 35 36 37 38 39 40 05h 41 42 43 44 45 46 47 48 06h 49 50 51 52 53 54 55 56 07h 57 58 59 60 61 62 63 64 08h 65 66 67 68 69 70 71 72 09h 73 74 75 76 77 78 79 80 0ah 8182838485868788 0bh 8990919293949596 0ch 979899100xxxx remark data of x address = 0ch :b7 to b4 are data, b3 to b0 are dont care.
data sheet s12694ej2v0ds00 24 m m m m pd16680 9. command 9.1 basic form command register (cr) command register (cr) address register (cr) command register (cr) extend select register (esr) x address (xad) y address (yad) data 1 (dt1) + ++ ++ ..... 9.2 command register the command registers basic configuration is as follows. msb lsb choices command type (0 x h to b x h) b7 b6 b5 b4 b3 b2 b1 b0 table 7-1 command table register command d7 d6 d5 d4 d3 d2 d1 d0 reset 00100111 display on/off 00001b2b1b0 standby 00010b2b1b0 d/a converter setting 00101000 duty setting 00011b3b2b0 blink setting 01000b2b1b0 data r/w mode 10110b2b1b0 test mode 10111b2b1b0
data sheet s12694ej2v0ds00 25 m m m m pd16680 9.2.1 reset the all ic's commands are initialized. msb lsb 001 0 0 111 9.2.2 display on/off on/off of the display is controlled. msb lsb 00001 b1b0 b2 choices 000 : lcd off (seg n , com n , pcom n = v ss ) 001 : lcd off (seg n , com n , pcom n = non-serective output) 111 : lcd on 9.2.3 standby the dc/dc converter is stopped, thus reducing the supply current. this display is placed in the off state (segn, comn = v ss ). even at standby, it is possible to write command and data. msb lsb 000 1 0 b2 b1 b0 000 : nomal operation 001 : standby (dc/dc converter halt, all display off , osc halt) cohices note note seg n , com n , pcom = v ss
data sheet s12694ej2v0ds00 26 m m m m pd16680 9.2.4 d/a converter setting the internal d/a converter is set. d/a converter output voltage is controlled from 1/2v dd to v dd . msb lsb 001 0 1 000 msb lsb 00 b4 b5 b3 b2 b1 b0 + extend choices d/a converter output voltage 00h(min.) to 3fh(max.) caution after resetting, it is set to 20h. 9.2.5 duty setting the duty is set. msb lsb choices 000 : 1/53 duty 001 : 1/40 duty 000 1 1 b2 b1 b0 note note if the duty cycle is 1/40, leave open from com 39 to com 51 . 9.2.6 blink setting the blinks of the pictograph of the address whose blink data is 1 are controlled. msb lsb choices 000 : blink halt 001 : blink start (blink frequency = f osc /32768) 010 : blink start (blink frequency = f bri /2) 010 0 0 b2 b1 b0 note note this refers to the frequency of the external clock which is input from the osc br1 pin.
data sheet s12694ej2v0ds00 27 m m m m pd16680 9.2.7 data r/w mode data read/write (r/w), increment, address counter resetting, etc. are set in this mode. msb lsb 101 1 0 b2 b1 b0 msb lsb b2 b3 b4 b5 b6 b7 b1 b0 ++ data . . . choices 1 00 : the address is incremented starting from the current one 01 : current address retained choices 2 0 : data writing 1 : data reading note1 note2 notes 1. when x address and y address goes to last address, next address is 00h. 2. the data read mode is canceled at stb's rising edge (switched to data write mode). remark when using serial data transfer, it is necessary to write 8-bit data. no assurance is ic's operation when stb is rising during data transfer. 9.2.8 test mode the test mode is set. the test mode is for checking ics operation, and no assurance is made for its regular use or continued operation. msb lsb 101 1 1 b2 b1 b0 choices 000 : nomal operation 001 to 111 : test mode
data sheet s12694ej2v0ds00 28 m m m m pd16680 9.3 address register selects the address type and specifies the address. msb lsb 11b5 b4 0 000 msb lsb 000 0 b3 b2 b1 b0 msb lsb 00b5 b4 b3 b2 b1 b0 ++ choice1 00 : dot address 01 : pictograph group address 10 : blink data group address x address dot display group address : 00h to 0ch pictograph group address : 00h to 0ch blink group address : 00h to 0ch y address dot display group address : 00h to 33h pictograph group address : 00h blink group address : 00h caution if unspecified addresses have been set, operation is not assured. 10. resetting when reset (command reset, hardware (terminal) reset), the contents of each register are as follows. register contents register name b7 b6 b5 b4 b3 b2 b1 b0 status display on / off 00001000lcd off (seg n , com n , pcom = v ss ) standby 0 0 0 1 0 0 0 0 normal operation duty setting 0 0 0 1 1 0 0 0 1/53 duty d/a converter setting 1 0 0 0 0 0 0 0 to set 20h blink setting 01000000blink halt data r/w mode 1 0 1 1 0 0 0 0 data write, the address is incremented(+1) starting from current address. test mode 1 0 1 1 1 0 0 0 normal operation h
data sheet s12694ej2v0ds00 29 m m m m pd16680 11. communication format 11.1 serial 11.1.1 reception 1 (command/data write : 1 byte) stb data sck b7 b6 b5 b2 b1 b0 12 3 67 8 11.1.2 reception 2 (command/data write : 2 bytes or more) b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3 123 67 8 1 2 3 45 stb data sck command 1 command 2/data 11.1.3 transmission (command/data read) b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3 123 67 8 123 4 5 6 stb data sck data read command wait time : t wait data read
data sheet s12694ej2v0ds00 30 m m m m pd16680 11.2 parallel 11.2.1 8-bit parallel interface stb d 0 to d 7 e 11.2.2 4-bit parallel interface stb d 0 to d 7 e upper upper upper lower lower lower
data sheet s12694ej2v0ds00 31 m m m m pd16680 12 cpu access example 12.1 initialize and write data command / data item stb b7 b6 b5 b4 b3 b2 b1 b0 explanation start h xxxxxxxx reset l 00100111 h xxxxxxxx duty setting l 0 0 0 1 1 0 0 0 1/53 duty h xxxxxxxx address register 1 l 1 1 0 0 0 0 0 0 dot address address register 2 l 0 0 0 0 0 0 0 0 x address = 00h address register 3 l 0 0 0 0 0 0 0 0 y address = 00h h xxxxxxxx data r/w mode l 10110000 data write, the address is incremented starting from the current one. dot display data 1 dot display data 663 l l d d d d d d d d d d d d d d d d dot data (63 bytes) h xxxxxxxx address register 1 l 1 1 0 1 0 0 0 0 pictograph group address address register 2 l 0 0 0 0 0 0 0 0 x address = 00h address register 3 l 0 0 0 0 0 0 0 0 y address = 00h h xxxxxxxx data r/w mode l 10110000 data write, the address is incremented starting from the current one. pictograph data 1 pictograph data 13 l l d d d d d d d d d d d d d d d d pictograph data (13 bytes) h xxxxxxxx display on / off l 00001111lcd on end h xxxxxxxx remark x = don't care, d = data
data sheet s12694ej2v0ds00 32 m m m m pd16680 12.2 change display data and pictograph data (all data are changed) command / data item stb b7 b6 b5 b4 b3 b2 b1 b0 explanation start h xxxxxxxx address register 1 l 1 1 0 0 0 0 0 0 dot address address register 2 l 0 0 0 0 0 0 0 0 x address = 00h address register 3 l 0 0 0 0 0 0 0 0 y address = 00h h xxxxxxxx data r/w mode l 10110000 data write, the address is incremented starting from the current one. dot display data 1 dot display data 663 l l d d d d d d d d d d d d d d d d dot data (663 bytes) h xxxxxxxx address register 1 l 1 1 0 1 0 0 0 0 pictograph group address address register 2 l 0 0 0 0 0 0 0 0 x address = 00h address register 3 l 0 0 0 0 0 0 0 0 y address = 00h h xxxxxxxx data r/w mode l 10110000 data write, the address is incremented starting from the current one. pictograph data 1 pictograph data 13 l l d d d d d d d d d d d d d d d d pictograph data (13 bytes) end h xxxxxxxx remark x = don't care, d = data
data sheet s12694ej2v0ds00 33 m m m m pd16680 12.3 read display data and pictograph data (all data are read) command / data item stb b7 b6 b5 b4 b3 b2 b1 b0 explanation start h xxxxxxxx address register 1 l 1 1 0 0 0 0 0 0 dot address address register 2 l 0 0 0 0 0 0 0 0 x address = 00h address register 3 l 0 0 0 0 0 0 0 0 y address = 00h h xxxxxxxx data r/w mode l 10110100 data read, the address is incremented starting from the current one. dot display data 1 dot display data 663 l l d d d d d d d d d d d d d d d d dot data (663 bytes) h xxxxxxxx address register 1 l 1 1 0 1 0 0 0 0 pictograph group address address register 2 l 0 0 0 0 0 0 0 0 x address = 00h address register 3 l 0 0 0 0 0 0 0 0 y address = 00h h xxxxxxxx data r/w mode l 10110100 data read, the address is incremented starting from the current one. pictograph data 1 pictograph data 13 l l d d d d d d d d d d d d d d d d pictograph data (13 bytes) end h xxxxxxxx remark x = don't care, d = data
data sheet s12694ej2v0ds00 34 m m m m pd16680 12.4 blink data setting command / data item stb b7 b6 b5 b4 b3 b2 b1 b0 explanation start h xxxxxxxx address register 1 l 1 1 1 0 0 0 0 0 blink group address address register 2 l 0 0 0 0 0 0 0 0 x address = 00h address register 3 l 0 0 0 0 0 0 0 0 y address = 00h h xxxxxxxx data r/w mode l 10110000 data write, the address is incremented starting from the current one. blink data 1 blink data 13 l l d d d d d d d d d d d d d d d d blink data (13 bytes) h xxxxxxxx blink setting l 0 1 0 0 0 0 1 0 blink start, blink frequency = f bri /2 end h xxxxxxxx remark x= don't care, d = data h h h
data sheet s12694ej2v0ds00 35 m m m m pd16680 13. electrical specifications absolute maximum ratings (t a =+25 c, v ss =0 v) parameter symbol ratings unit supply voltage (4-fold voltage mode) v dd C0.3 to +3.75 v supply voltage (3-fold voltage mode) v dd C0.3 to +5.0 v driver supply voltage v lcd C0.3 to +15.0, v dd v lcd v driver reference supply input voltage v lc1 to v lc5 C0.3 to v lcd +0.3 v logic system input voltage v in1 C0.3 to v dd +0.3 v logic system output voltage v out1 C0.3 to v dd +0.3 v logic system input/output voltage v i/01 C0.3 to v dd +0.3 v driver system input voltage v in2 C0.3 to v lcd +0.3 v driver system output voltage v out2 C0.3 to v lcd +0.3 v operating temperature t a C40 to +85 c storage temperature t stg C55 to +150 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range parameter symbol min. typ. max. unit supply voltage (4-fold voltage mode) v dd 2.4 3.0 v supply voltage (3-fold voltage mode) v dd 2.4 4.0 v driver supply voltage note v lcd 5.0 10 12 v logic system input voltage v in 0v dd v driver system input voltage v lc1 to v lc5 0v lcd v note when to use external lcd driving, this parameter is recommended. remarks1. when to use external lcd driving, keep v ss < v lc5 < v lc4 < v lc3 < v lc2 < v lc1 v lcd 2. when power on or power off moment, keep v dd v lcd 3. when to use internal lcd driving circuit and not to use d/a converter, keep voltage inputted to amp in(+) pin to 1.0v to v dd .
data sheet s12694ej2v0ds00 36 m m m m pd16680 electrical characteristics (unless otherwise specified, t a = C40 to +85 c, 4-fold voltage mode : v dd = 2.7 to 3.0v or 3-fold voltage mode : v dd = 2.7 to 4.0 v) parameter symbol conditions min. typ. max. unit high-level input voltage v ih 0.8 v dd v low-level input voltage v il 0.2 v dd v high-level input current i ih1 except d o /data, d 1 to d 7 1 m a low-level input current i il1 except d o /data, d 1 to d 7 C1 m a high-level output voltage v oh i out = C1.5 ma, except osc out v dd C0.5 v low-level output voltage v ol i out = 4 ma, except osc out 0.5 v high-level leakage current i loh d o /data, d 1 to d 7 v in/out = v dd 10 m a low -level leakage current i lol d o /data, d 1 to d 7 v in/out = v ss C10 m a common output on resistance r com v lcn ? com n , v lcd 3 3v dd li o l = 50 m a 2k w segment output on resistance r seg v lcn ? seg n , v lcd 3 3v dd li o l = 50 m a 4k w 3-fold voltage mode 2.7 v dd 3.0 v dd v driver voltage (booster voltage) v lcd 4-fold voltage mode 3.6 v dd 4.0 v dd v f osc = 32 khz, display-off data output v dd = 3.0 v,3-fold voltage mode not to access to ram. 95 m a current consumption (v dd ) level condenser mode i dd11 f osc = 32 khz, display-off data output v dd = 3.0 v,4-fold voltage mode not to access to ram. 125 m a f osc = 32 khz, display-off data output v dd = 3.0 v,3-fold voltage mode not to access to ram. 160 m a current consumption (v dd ) lcd driving mode i dd12 f osc = 32 khz, display-off data output v dd = 3.0 v,4-fold voltage mode not to access to ram. 250 m a driver current consumption (v dd , standby) i dd21 v dd = 3.0 v 10 m a h h h h
data sheet s12694ej2v0ds00 37 m m m m pd16680 switching characteristics (unless otherwise specified, t a = C40 to +85 c, v dd = 2.7 to 3.3 v) parameter symbol conditions min. typ. max. unit oscillation frequency f osc self-oscillation 25 32 38 khz transfer delay time 1 t phl sck ? data 100 ns transfer delay time 2 t plh sck ? data - 300 ns remarks 1. the typ. value is a reference value when t a =+25 c. 2. the time for one frame is found from the following formula. 1 frame = 1/fosc x 8 x number of duties (example) f osc = 32 khz, 1/53, then the result is : 1 frame = 33 m s x 8 x 53 = 13.25 ms @ 75.5 hz h
data sheet s12694ej2v0ds00 38 m m m m pd16680 required conditions for timing (unless otherwise specified, t a = C40 to +85 c, v dd = 2.7 to 3.3 v) 1. common parameter symbol conditions min. typ. max. unit clock frequency f osc osc in external clock 20 32 50 khz high-level clock pulse width t whc1 osc in external clock 10 25 m s low -level clock pulse width t wlc1 osc in external clock 10 25 m s high-level clock pulse width t whc2 osc bri external clock 400 ns low -level clock pulse width t wlc2 osc bri external clock 400 ns rise/fall time t r , t f osc bri external clock 100 ns reset pulse width t wre /reset pin 50 m s remark the typ. value is a reference value when t a =+25 c. 2. serial interface parameter synbol conditions min. typ. max. unit shift clock cycle t cyk sck 900 ns high-level shift clock pulse width t whk sck 295 ns low-level shift clock pulse width t wlk sck 295 ns shift clock hold time t hstbk stb ? sck 400 ns data setup time t ds1 data ? sck - 40 ns data hold time t dh1 sck - ? data 40 ns stb hold time t hkstb sck - ? stb - 400 ns stb pulse width t wstb 210 ns wait time note t wait 8th clk - ? 1st clk 100 ns note see 11.1.3 transmission (command/data read) . 3. parallel interface parameter symbol conditions min. typ. max. unit enable cycle time t cyce e - ? e - 900 ns high-level enable pulse width t whe e 295 ns low-level enable pulse width t wle e 295 ns stb pulse width t wstb 210 ns stb hold time t hkstb 400 ns enable hold time t hstbk 400 ns data setup time t ds2 d 0 to d 7 ? e - 40 ns data hold time t dh2 d 0 to d 7 ? e 40 ns
data sheet s12694ej2v0ds00 39 m m m m pd16680 switching characteristics waveforms ac measurement point v ih v il v oh v ol input output ac characteristics waveform t whc1 t wlc1 1/f osc t whc2 t wlc2 t f t r osc in osc br1 serial interface (input) t ds1 t dh1 t whk t cyk t wstb t hstbk t hkstb stb sck data serial interface (output) sck data t phl t plh
data sheet s12694ej2v0ds00 40 m m m m pd16680 4-bit parallel interface stb e d n stb e d n t hstbk t wle t whe t cyce t dh2 t ds2 t wstb t hkstb upper bit upper bit upper bit upper bit lower bit lower bit 8-bit parallel interface stb e d n t hstbk t wle t whe t cyce t dh2 t ds2 t wstb t hkstb reset t wre /reset
data sheet s12694ej2v0ds00 41 m m m m pd16680 [memo]
data sheet s12694ej2v0ds00 42 m m m m pd16680 [memo]
data sheet s12694ej2v0ds00 43 m m m m pd16680 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16680 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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